Hi!
WillTrojak September 4 Thanks Segher. Yeah that’s what I was doing. But I was thinking that maybe if something was added as an extended mnemonic to the ISA, then it would mean tools like objdump could interpret the pnop with a non-zero value
Thanks Segher. Yeah that’s what I was doing. But I was thinking that maybe if something was added as an extended mnemonic to the ISA, then it would mean tools like objdump could interpret the pnop with a non-zero value as a tag and even the assembler could generate these pnops?
Hrm. The insn with payload should be the base instruction, and the one with everything zero (so “pnop”) an extended mnemonic, then.
I think if you want to avoid those 3 cases, you can do that by enforcing that bit 0-5 of the second word are zero? (Although I think bits 0-5 on the effected instructions are only 17, 19, or 31, so that wouldn’t be too hard to filter).
You can simply outlaw all of primary ops 16…19, as well as attn.
That will unnecessarily disallow crlogicals and addpcis, but that’s about it. Allowing the first half of primary 19 again will make this better (but less regular).
You cannot just decide to always use small numbers, because attn is one (it is hex 100).
For example 0x0700000000000001
currently resolves as
00: 00 00 00 07 pnop
04: 01 00 00 00
but maybe it could be something like
00: 00 00 00 07 pnop 1
04: 01 00 00 00
or even
00: 00 00 00 07 tag 1
04: 01 00 00 00
Just a shower thought, but these might even be useful if you want to sneak a 32-bit constant to be used but want to avoid the potential penalty of cache miss from reading from a data region.
Ah, have pnop both as an extended mnemonic and as a base one, if it has no args. Works for me!
Segher
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